1. Field of the Invention
The present invention relates to semiconductor device structures, but more specifically, the present invention relates to an improved permeable base transistor structure.
2. Description of the Prior Art
FIG. 1 is an isometric/cutaway view of a conventional permeable base transistor (PBT) structure 10. It may be thought of as a practical implementation of the metal base transistor or as a perfection of the gridistor of the 1960s. Conventional PBT structure 10 comprises a metal ohmic emitter/cathode/source contact 12, and a control grid structure 14 including a plurality of control grid fingers 16 and a control grid contact 18 integral thereto. Conventional PBT structure 10 further includes an n.sup.+ GaAs substrate 20 upon which a collector/anode/drain region 22 of n-type semiconductor material is grown (epitaxially deposited) over the plurality of control grid fingers 16 of the control grid structure 14. Finally, collector/anode/drain ohmic contact 24 is fixed to the top of collector/anode/drain region 22, aforementioned. A model developed for conventional PBT structure 10 has shown it to be superior, in amplifier applications, to all other three terminal solid state structures. The model predicts operation to frequencies exceeding 200 GHz. While operation has been reported at K-band frequencies, this performance has not been reproducible and prospects for reaching 100 GHz with the present structure are not promising.
It has been determined that a significant part of the difficulty experienced has been due to the quality of the semiconductor material immediately adjacent to the control grid structure 14. To overcome this problem, attempts have been made to grow the entire semiconductor portion of the device, etch deep "trenches" for the grid, deposit the grid metal in the bottom of the trenches, cover the grid and fill the trenches with semiconductor material, and deposit an ohmic contact. Results, to date have not been promising. Other approaches simply do not bother to backfill the trenches above the grid metal, and, consequentially, the resultant structure is a vertical channel transistor.
Still referring to FIG. 1, a current version of conventional PBT structure 10 uses semiconductor material such as epitaxially deposited GaAs 26 of the same conductivity on both sides (lower and upper) of control grid fingers 16 grown on n.sup.+ GaAs substrate 20. To ensure a reasonable depletion depth adjacent to control grid fingers 16, the semiconductor doping density must not exceed 5.times.10.sup.16 cm.sup.-3. While this doping density is nearly ideal for the region between control grid fingers 16 and collector/anode/drain ohmic contact 24, it introduces excessive resistance in the channel region between control grid fingers 16, and metal ohmic emitter/cathode/source contact 12. This resistance introduces negative feedback and lowers the gain of any device fabricated according to conventional PBT structure 10. Increasing the doping density in the aforementioned channel region in order to reduce negative feedback has a counterproductive effect, i.e., parasitic losses increase in the region of control grid fingers 16.
The region immediately above each one of the plurality of control grid fingers 16 has typically been backfilled with polycrystalline GaAs (not shown) so as to ease the task of applying an ohmic contact such as collector/anode/drain ohmic contact 24. Without the polycrystalline GaAs backfill, the ohmic contacting material tends to short out control grid fingers 16. This backfill material, however, introduces parasitic losses by virtue of its immediate proximity to control grid fingers 16.
While control grid parasitics and the excessive negative feedback in the channel region between control grid fingers 16 and metal ohmic emitter/cathode/source contact 12 will probably preclude further performance improvements in conventional PBT structure 10, its basic geometry consumes less than 1/16 of the GaAs "real estate" required of an FET with similar control circuit periphery. This aspect is particularly relevant for operation at frequencies above 20 GHz where present planar FET structures require control gate lateral dimensions which are significant portions of a wavelength.